hydra-eclipse / sysml2vhdlams

Blame view

Examples/CircuitRC/Models/CircuitRC.vhdlamsmodel 6.74 KB
edit raw normal view history
f902ce56c   Jean-Marie Gauthier   Commit of projects 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
 
  <?xml version="1.0" encoding="ISO-8859-1"?>
  <xmi:XMI xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vhdlams="http://www.femto-st.fr/disc/vhdlams.ecore">
    <vhdlams:VAModel name="CircuitRC">
      <package name="CircuitRC">
        <designUnit xsi:type="vhdlams:Entity" comment="/0/@package.2/@designUnit.1" name="Resistor" architecture="/0/@package.0/@designUnit.1">
          <property xsi:type="vhdlams:Generic" name="R">
            <type href="pathmap://VHDLAMS_LIBRARIES/vhdlPrimitive.vhdl.xmi#//@designUnit.0/@designUnit.0"/>
          </property>
          <property xsi:type="vhdlams:Terminal" name="m">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
          <property xsi:type="vhdlams:Terminal" name="p">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
        </designUnit>
        <designUnit xsi:type="vhdlams:Architecture" name="behav" entity="/0/@package.0/@designUnit.0">
          <property xsi:type="vhdlams:BranchQuantity" plus_terminal="/0/@package.0/@designUnit.0/@property.2" minus_terminal="/0/@package.0/@designUnit.0/@property.1" through="/2" across="/1"/>
          <statement xsi:type="vhdlams:ConcurrentialStatement" body="v_in == R * i_out"/>
        </designUnit>
        <designUnit xsi:type="vhdlams:Entity" comment="/0/@package.2/@designUnit.2" name="Condensateur" architecture="/0/@package.0/@designUnit.3">
          <property xsi:type="vhdlams:Generic" name="C">
            <type href="pathmap://VHDLAMS_LIBRARIES/vhdlPrimitive.vhdl.xmi#//@designUnit.0/@designUnit.0"/>
          </property>
          <property xsi:type="vhdlams:Terminal" name="m">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
          <property xsi:type="vhdlams:Terminal" name="p">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
        </designUnit>
        <designUnit xsi:type="vhdlams:Architecture" name="behav" entity="/0/@package.0/@designUnit.2">
          <property xsi:type="vhdlams:BranchQuantity" plus_terminal="/0/@package.0/@designUnit.2/@property.2" minus_terminal="/0/@package.0/@designUnit.2/@property.1" through="/4" across="/3"/>
          <statement xsi:type="vhdlams:ConcurrentialStatement" body="i_out == C * v_in'dot"/>
        </designUnit>
        <designUnit xsi:type="vhdlams:Entity" name="Generateur" architecture="/0/@package.0/@designUnit.5">
          <property xsi:type="vhdlams:Terminal" name="m">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
          <property xsi:type="vhdlams:Terminal" name="p">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
        </designUnit>
        <designUnit xsi:type="vhdlams:Architecture" name="behav" entity="/0/@package.0/@designUnit.4">
          <property xsi:type="vhdlams:Constant" name="v" default="110.0">
            <type href="pathmap://VHDLAMS_LIBRARIES/vhdlPrimitive.vhdl.xmi#//@designUnit.0/@designUnit.0"/>
          </property>
          <property xsi:type="vhdlams:BranchQuantity" plus_terminal="/0/@package.0/@designUnit.4/@property.1" minus_terminal="/0/@package.0/@designUnit.4/@property.0" through="/6" across="/5"/>
          <statement xsi:type="vhdlams:ConcurrentialStatement" body="v_in == v"/>
        </designUnit>
        <designUnit xsi:type="vhdlams:Entity" comment="/0/@package.2/@designUnit.0" name="Circuit" architecture="/0/@package.0/@designUnit.7"/>
        <designUnit xsi:type="vhdlams:Architecture" name="behav" entity="/0/@package.0/@designUnit.6">
          <property xsi:type="vhdlams:Terminal" name="n1">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
          <property xsi:type="vhdlams:Terminal" name="n2">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.12"/>
          </property>
          <property xsi:type="vhdlams:Terminal" name="ground">
            <type href="pathmap://VHDLAMS_LIBRARIES/ieee.vhdl.xmi#//@designUnit.7/@designUnit.10"/>
          </property>
          <statement xsi:type="vhdlams:ComponentInstanciation" name="R1" type="/0/@package.0/@designUnit.0" architecture="/0/@package.0/@designUnit.1">
            <map xsi:type="vhdlams:PortMap" from="/0/@package.0/@designUnit.0/@property.2" to="/0/@package.0/@designUnit.7/@property.0"/>
            <map xsi:type="vhdlams:PortMap" from="/0/@package.0/@designUnit.0/@property.1" to="/0/@package.0/@designUnit.7/@property.1"/>
            <map xsi:type="vhdlams:GenericMap" from="/0/@package.0/@designUnit.0/@property.0" to="/7"/>
          </statement>
          <statement xsi:type="vhdlams:ComponentInstanciation" name="C1" type="/0/@package.0/@designUnit.2" architecture="/0/@package.0/@designUnit.3">
            <map xsi:type="vhdlams:PortMap" from="/0/@package.0/@designUnit.2/@property.2" to="/0/@package.0/@designUnit.7/@property.1"/>
            <map xsi:type="vhdlams:PortMap" from="/0/@package.0/@designUnit.2/@property.1" to="/0/@package.0/@designUnit.7/@property.2"/>
            <map xsi:type="vhdlams:GenericMap" from="/0/@package.0/@designUnit.2/@property.0" to="/8"/>
          </statement>
          <statement xsi:type="vhdlams:ComponentInstanciation" name="SRC" type="/0/@package.0/@designUnit.4" architecture="/0/@package.0/@designUnit.5">
            <map xsi:type="vhdlams:PortMap" from="/0/@package.0/@designUnit.4/@property.1" to="/0/@package.0/@designUnit.7/@property.0"/>
            <map xsi:type="vhdlams:PortMap" from="/0/@package.0/@designUnit.4/@property.0" to="/0/@package.0/@designUnit.7/@property.2"/>
          </statement>
        </designUnit>
      </package>
      <package name="Constraint"/>
      <package name="Requirements">
        <designUnit xsi:type="vhdlams:Comment" element="/0/@package.0/@designUnit.6" description="-- @Req1.0 'Requirement1' : The system shall be capable to do a low-pass band filter"/>
        <designUnit xsi:type="vhdlams:Comment" element="/0/@package.0/@designUnit.0" description="-- @Req1.1 'Requirement2' : The system shall be capable to have a derivator behavior"/>
        <designUnit xsi:type="vhdlams:Comment" element="/0/@package.0/@designUnit.2" description="-- @Req1.2 'Requirement3' : The system shall be capable to respond in 2ms"/>
      </package>
      <library name="IEEE">
        <use name="electrical_systems"/>
      </library>
    </vhdlams:VAModel>
    <vhdlams:Variable name="v_in"/>
    <vhdlams:Variable name="i_out"/>
    <vhdlams:Variable name="v_in"/>
    <vhdlams:Variable name="i_out"/>
    <vhdlams:Variable name="v_in"/>
    <vhdlams:Variable name="i_out"/>
    <vhdlams:Expression body="100.0"/>
    <vhdlams:Expression body="1.0e-6"/>
  </xmi:XMI>